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DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
Figure 2. Memory Map
ADDRESS
000h to 03Fh
040h to 07Fh
080h to 0BFh
0C0h to 0FFh
100h to 109h
10Ah
10Bh
10Ch
10Dh
10Eh
TYPE
EEPROM
EEPROM
EEPROM
EEPROM
—
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
ACCESS
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
DESCRIPTION
User memory block 0.
User memory block 1.
User memory block 2.
User memory block 3.
Reserved, contents undefined.
Power-on default for PIO output state (PIO0 to PIO7).
Power-on default for PIO output state (PIO8 to PIO11).
Power-on default for PIO direction (PIO0 to PIO7).
Power-on default for PIO direction (PIO8 to PIO11).
Power-on default for PIO read-inversion (PIO0 to PIO7).
Power-on default for PIO read-inversion (PIO8 to PIO11),
10Fh
EEPROM
R/W
PIO output type (PIO0 to PIO11 in groups of 4 PIOs), PIO
output mode (same mode for all PIOs).
110h to 117h
118h to 11Fh
120h
121h
122h
123h
124h
—
ROM
SRAM
SRAM
SRAM
SRAM
SRAM
—
R
R/W
R/W
R/W
R/W
R/W
Reserved, contents is undefined.
64-bit unique registration number.
PIO output state (PIO0 to PIO7).
PIO output state (PIO8 to PIO11).
PIO direction (PIO0 to PIO7).
PIO direction (PIO8 to PIO11).
PIO read-inversion (PIO0 to PIO7).
PIO read-inversion (PIO8 to PIO11), PIO output type (PIO0
125h
SRAM
R/W
to PIO11 in groups of 4 PIOs), PIO output mode (same
mode for all PIOs).
126h
127h
128h
129h to 12Fh
130h to 133h
134h
135h
136h and above
—
—
—
NV SRAM
NV SRAM
NV SRAM
NV SRAM
—
R
R
—
R/W
R/W
R/W
R/Clear
—
PIO read access (PIO0 to PIO7).
PIO read access (PIO8 to PIO11).
Reserved, contents undefined.
RTC and calendar.
RTC alarm.
Multifunction control/setup register.
Alarm and status register.
Reserved, contents undefined.
7 of 34
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